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Building External Modules¶

This document describes how to build an out-of-tree kernel module.

1. Introduction¶

“kbuild” is the build system used by the Linux kernel. Modules must use kbuild to stay compatible with changes in the build infrastructure and to pick up the right flags to “gcc.” Functionality for building modules both in-tree and out-of-tree is provided. The method for building either is similar, and all modules are initially developed and built out-of-tree.

Covered in this document is information aimed at developers interested in building out-of-tree (or “external”) modules. The author of an external module should supply a makefile that hides most of the complexity, so one only has to type “make” to build the module. This is easily accomplished, and a complete example will be presented in section 3.

2. How to Build External Modules¶

To build external modules, you must have a prebuilt kernel available that contains the configuration and header files used in the build. Also, the kernel must have been built with modules enabled. If you are using a distribution kernel, there will be a package for the kernel you are running provided by your distribution.

An alternative is to use the “make” target “modules_prepare.” This will make sure the kernel contains the information required. The target exists solely as a simple way to prepare a kernel source tree for building external modules.

NOTE: “modules_prepare” will not build Module.symvers even if CONFIG_MODVERSIONS is set; therefore, a full kernel build needs to be executed to make module versioning work.

2.1 Command Syntax¶

The command to build an external module is:

The kbuild system knows that an external module is being built due to the “M= ” option given in the command.

To build against the running kernel use:

Then to install the module(s) just built, add the target “modules_install” to the command:

2.2 Options¶

($KDIR refers to the path of the kernel source directory.)

make -C $KDIR M=$PWD

The directory where the kernel source is located. “make” will actually change to the specified directory when executing and will change back when finished.

Informs kbuild that an external module is being built. The value given to “M” is the absolute path of the directory where the external module (kbuild file) is located.

2.3 Targets¶

When building an external module, only a subset of the “make” targets are available.

make -C $KDIR M=$PWD [target]

The default will build the module(s) located in the current directory, so a target does not need to be specified. All output files will also be generated in this directory. No attempts are made to update the kernel source, and it is a precondition that a successful “make” has been executed for the kernel.

The default target for external modules. It has the same functionality as if no target was specified. See description above.

Install the external module(s). The default location is /lib/modules/ /extra/, but a prefix may be added with INSTALL_MOD_PATH (discussed in section 5).

Remove all generated files in the module directory only.

List the available targets for external modules.

2.4 Building Separate Files¶

It is possible to build single files that are part of a module. This works equally well for the kernel, a module, and even for external modules.

Example (The module foo.ko, consist of bar.o and baz.o):

3. Creating a Kbuild File for an External Module¶

In the last section we saw the command to build a module for the running kernel. The module is not actually built, however, because a build file is required. Contained in this file will be the name of the module(s) being built, along with the list of requisite source files. The file may be as simple as a single line:

The kbuild system will build .o from .c, and, after linking, will result in the kernel module .ko. The above line can be put in either a “Kbuild” file or a “Makefile.” When the module is built from multiple sources, an additional line is needed listing the files:

NOTE: Further documentation describing the syntax used by kbuild is located in Linux Kernel Makefiles .

The examples below demonstrate how to create a build file for the module 8123.ko, which is built from the following files:

3.1 Shared Makefile¶

An external module always includes a wrapper makefile that supports building the module using “make” with no arguments. This target is not used by kbuild; it is only for convenience. Additional functionality, such as test targets, can be included but should be filtered out from kbuild due to possible name clashes.

The check for KERNELRELEASE is used to separate the two parts of the makefile. In the example, kbuild will only see the two assignments, whereas “make” will see everything except these two assignments. This is due to two passes made on the file: the first pass is by the “make” instance run on the command line; the second pass is by the kbuild system, which is initiated by the parameterized “make” in the default target.

3.2 Separate Kbuild File and Makefile¶

In newer versions of the kernel, kbuild will first look for a file named “Kbuild,” and only if that is not found, will it then look for a makefile. Utilizing a “Kbuild” file allows us to split up the makefile from example 1 into two files:

The split in example 2 is questionable due to the simplicity of each file; however, some external modules use makefiles consisting of several hundred lines, and here it really pays off to separate the kbuild part from the rest.

The next example shows a backward compatible version.

Here the “Kbuild” file is included from the makefile. This allows an older version of kbuild, which only knows of makefiles, to be used when the “make” and kbuild parts are split into separate files.

3.3 Binary Blobs¶

Some external modules need to include an object file as a blob. kbuild has support for this, but requires the blob file to be named _shipped. When the kbuild rules kick in, a copy of _shipped is created with _shipped stripped off, giving us . This shortened filename can be used in the assignment to the module.

Throughout this section, 8123_bin.o_shipped has been used to build the kernel module 8123.ko; it has been included as 8123_bin.o:

Although there is no distinction between the ordinary source files and the binary file, kbuild will pick up different rules when creating the object file for the module.

3.4 Building Multiple Modules¶

kbuild supports building multiple modules with a single build file. For example, if you wanted to build two modules, foo.ko and bar.ko, the kbuild lines would be:

It is that simple!

4. Include Files¶

Within the kernel, header files are kept in standard locations according to the following rule:

If the header file only describes the internal interface of a module, then the file is placed in the same directory as the source files.

If the header file describes an interface used by other parts of the kernel that are located in different directories, then the file is placed in include/linux/.

There are two notable exceptions to this rule: larger subsystems have their own directory under include/, such as include/scsi; and architecture specific headers are located under arch/$(SRCARCH)/include/.

4.1 Kernel Includes¶

To include a header file located under include/linux/, simply use:

kbuild will add options to “gcc” so the relevant directories are searched.

4.2 Single Subdirectory¶

External modules tend to place header files in a separate include/ directory where their source is located, although this is not the usual kernel style. To inform kbuild of the directory, use either ccflags-y or CFLAGS_ .o.

Using the example from section 3, if we moved 8123_if.h to a subdirectory named include, the resulting kbuild file would look like:

Note that in the assignment there is no space between -I and the path. This is a limitation of kbuild: there must be no space present.

4.3 Several Subdirectories¶

kbuild can handle files that are spread over several directories. Consider the following example:

To build the module complex.ko, we then need the following kbuild file:

As you can see, kbuild knows how to handle object files located in other directories. The trick is to specify the directory relative to the kbuild file’s location. That being said, this is NOT recommended practice.

For the header files, kbuild must be explicitly told where to look. When kbuild executes, the current directory is always the root of the kernel tree (the argument to “-C”) and therefore an absolute path is needed. $(src) provides the absolute path by pointing to the directory where the currently executing kbuild file is located.

5. Module Installation¶

Modules which are included in the kernel are installed in the directory:

And external modules are installed in:

5.1 INSTALL_MOD_PATH¶

Above are the default directories but as always some level of customization is possible. A prefix can be added to the installation path using the variable INSTALL_MOD_PATH:

INSTALL_MOD_PATH may be set as an ordinary shell variable or, as shown above, can be specified on the command line when calling “make.” This has effect when installing both in-tree and out-of-tree modules.

5.2 INSTALL_MOD_DIR¶

External modules are by default installed to a directory under /lib/modules/$(KERNELRELEASE)/extra/, but you may wish to locate modules for a specific functionality in a separate directory. For this purpose, use INSTALL_MOD_DIR to specify an alternative name to “extra.”:

6. Module Versioning¶

Module versioning is enabled by the CONFIG_MODVERSIONS tag, and is used as a simple ABI consistency check. A CRC value of the full prototype for an exported symbol is created. When a module is loaded/used, the CRC values contained in the kernel are compared with similar values in the module; if they are not equal, the kernel refuses to load the module.

Module.symvers contains a list of all exported symbols from a kernel build.

6.1 Symbols From the Kernel (vmlinux + modules)В¶

During a kernel build, a file named Module.symvers will be generated. Module.symvers contains all exported symbols from the kernel and compiled modules. For each symbol, the corresponding CRC value is also stored.

The syntax of the Module.symvers file is:

The fields are separated by tabs and values may be empty (e.g. if no namespace is defined for an exported symbol).

For a kernel build without CONFIG_MODVERSIONS enabled, the CRC would read 0x00000000.

Module.symvers serves two purposes:

It lists all exported symbols from vmlinux and all modules.

It lists the CRC if CONFIG_MODVERSIONS is enabled.

6.2 Symbols and External Modules¶

When building an external module, the build system needs access to the symbols from the kernel to check if all external symbols are defined. This is done in the MODPOST step. modpost obtains the symbols by reading Module.symvers from the kernel source tree. During the MODPOST step, a new Module.symvers file will be written containing all exported symbols from that external module.

6.3 Symbols From Another External Module¶

Sometimes, an external module uses exported symbols from another external module. Kbuild needs to have full knowledge of all symbols to avoid spitting out warnings about undefined symbols. Two solutions exist for this situation.

NOTE: The method with a top-level kbuild file is recommended but may be impractical in certain situations.

Use a top-level kbuild file

If you have two modules, foo.ko and bar.ko, where foo.ko needs symbols from bar.ko, you can use a common top-level kbuild file so both modules are compiled in the same build. Consider the following directory layout:

The top-level kbuild file would then look like:

will then do the expected and compile both modules with full knowledge of symbols from either module.

Use “make” variable KBUILD_EXTRA_SYMBOLS

If it is impractical to add a top-level kbuild file, you can assign a space separated list of files to KBUILD_EXTRA_SYMBOLS in your build file. These files will be loaded by modpost during the initialization of its symbol tables.

7. Tips & Tricks¶

7.1 Testing for CONFIG_FOO_BAR¶

Modules often need to check for certain CONFIG_ options to decide if a specific feature is included in the module. In kbuild this is done by referencing the CONFIG_ variable directly:

External modules have traditionally used “grep” to check for specific CONFIG_ settings directly in .config. This usage is broken. As introduced before, external modules should use kbuild for building and can therefore use the same methods as in-tree modules when testing for CONFIG_ definitions.

© Copyright The kernel development community.

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Linux Kernel Makefiles¶

This document describes the Linux kernel Makefiles.

1 Overview¶

The Makefiles have five parts:

The top Makefile reads the .config file, which comes from the kernel configuration process.

The top Makefile is responsible for building two major products: vmlinux (the resident kernel image) and modules (any module files). It builds these goals by recursively descending into the subdirectories of the kernel source tree. The list of subdirectories which are visited depends upon the kernel configuration. The top Makefile textually includes an arch Makefile with the name arch/$(ARCH)/Makefile. The arch Makefile supplies architecture-specific information to the top Makefile.

Each subdirectory has a kbuild Makefile which carries out the commands passed down from above. The kbuild Makefile uses information from the .config file to construct various file lists used by kbuild to build any built-in or modular targets.

scripts/Makefile.* contains all the definitions/rules etc. that are used to build the kernel based on the kbuild makefiles.

2 Who does what¶

People have four different relationships with the kernel Makefiles.

Users are people who build kernels. These people type commands such as «make menuconfig» or «make». They usually do not read or edit any kernel Makefiles (or any other source files).

Normal developers are people who work on features such as device drivers, file systems, and network protocols. These people need to maintain the kbuild Makefiles for the subsystem they are working on. In order to do this effectively, they need some overall knowledge about the kernel Makefiles, plus detailed knowledge about the public interface for kbuild.

Arch developers are people who work on an entire architecture, such as sparc or ia64. Arch developers need to know about the arch Makefile as well as kbuild Makefiles.

Kbuild developers are people who work on the kernel build system itself. These people need to know about all aspects of the kernel Makefiles.

This document is aimed towards normal developers and arch developers.

3 The kbuild files¶

Most Makefiles within the kernel are kbuild Makefiles that use the kbuild infrastructure. This chapter introduces the syntax used in the kbuild makefiles. The preferred name for the kbuild files are ‘Makefile’ but ‘Kbuild’ can be used and if both a ‘Makefile’ and a ‘Kbuild’ file exists, then the ‘Kbuild’ file will be used.

Section 3.1 «Goal definitions» is a quick intro, further chapters provide more details, with real examples.

3.1 Goal definitions¶

Goal definitions are the main part (heart) of the kbuild Makefile. These lines define the files to be built, any special compilation options, and any subdirectories to be entered recursively.

The most simple kbuild makefile contains one line:

This tells kbuild that there is one object in that directory, named foo.o. foo.o will be built from foo.c or foo.S.

If foo.o shall be built as a module, the variable obj-m is used. Therefore the following pattern is often used:

$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module). If CONFIG_FOO is neither y nor m, then the file will not be compiled nor linked.

3.2 Built-in object goals — obj-yВ¶

The kbuild Makefile specifies object files for vmlinux in the $(obj-y) lists. These lists depend on the kernel configuration.

Kbuild compiles all the $(obj-y) files. It then calls «$(AR) rcSTP» to merge these files into one built-in.a file. This is a thin archive without a symbol table. It will be later linked into vmlinux by scripts/link-vmlinux.sh

The order of files in $(obj-y) is significant. Duplicates in the lists are allowed: the first instance will be linked into built-in.a and succeeding instances will be ignored.

Link order is significant, because certain functions ( module_init() / __initcall) will be called during boot in the order they appear. So keep in mind that changing the link order may e.g. change the order in which your SCSI controllers are detected, and thus your disks are renumbered.

3.3 Loadable module goals — obj-mВ¶

$(obj-m) specifies object files which are built as loadable kernel modules.

A module may be built from one source file or several source files. In the case of one source file, the kbuild makefile simply adds the file to $(obj-m).

Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to ‘m’

If a kernel module is built from several source files, you specify that you want to build a module in the same way as above; however, kbuild needs to know which object files you want to build your module from, so you have to tell it by setting a $( -y) variable.

In this example, the module name will be isdn.o. Kbuild will compile the objects listed in $(isdn-y) and then run «$(LD) -r» on the list of these files to generate isdn.o.

Due to kbuild recognizing $( -y) for composite objects, you can use the value of a CONFIG_ symbol to optionally include an object file as part of a composite object.

In this example, xattr.o, xattr_user.o and xattr_trusted.o are only part of the composite object ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to ‘y’.

Note: Of course, when you are building objects into the kernel, the syntax above will also work. So, if you have CONFIG_EXT2_FS=y, kbuild will build an ext2.o file for you out of the individual parts and then link this into built-in.a, as you would expect.

3.4 Objects which export symbols¶

3.5 Library file goals — lib-yВ¶

Objects listed with obj-* are used for modules, or combined in a built-in.a for that specific directory. There is also the possibility to list objects that will be included in a library, lib.a. All objects listed with lib-y are combined in a single library for that directory. Objects that are listed in obj-y and additionally listed in lib-y will not be included in the library, since they will be accessible anyway. For consistency, objects listed in lib-m will be included in lib.a.

Note that the same kbuild makefile may list files to be built-in and to be part of a library. Therefore the same directory may contain both a built-in.a and a lib.a file.

This will create a library lib.a based on delay.o. For kbuild to actually recognize that there is a lib.a being built, the directory shall be listed in libs-y.

See also «6.4 List directories to visit when descending».

Use of lib-y is normally restricted to lib/ and arch/*/lib .

3.6 Descending down in directories¶

A Makefile is only responsible for building objects in its own directory. Files in subdirectories should be taken care of by Makefiles in these subdirs. The build system will automatically invoke make recursively in subdirectories, provided you let it know of them.

To do so, obj-y and obj-m are used. ext2 lives in a separate directory, and the Makefile present in fs/ tells kbuild to descend down using the following assignment.

If CONFIG_EXT2_FS is set to either ‘y’ (built-in) or ‘m’ (modular) the corresponding obj- variable will be set, and kbuild will descend down in the ext2 directory. Kbuild only uses this information to decide that it needs to visit the directory, it is the Makefile in the subdirectory that specifies what is modular and what is built-in.

It is good practice to use a CONFIG_ variable when assigning directory names. This allows kbuild to totally skip the directory if the corresponding CONFIG_ option is neither ‘y’ nor ‘m’.

3.7 Compilation flags¶

These three flags apply only to the kbuild makefile in which they are assigned. They are used for all the normal cc, as and ld invocations happening during a recursive build. Note: Flags with the same behaviour were previously named: EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS. They are still supported but their usage is deprecated.

ccflags-y specifies options for compiling with $(CC).

This variable is necessary because the top Makefile owns the variable $(KBUILD_CFLAGS) and uses it for compilation flags for the entire tree.

asflags-y specifies assembler options.

ldflags-y specifies options for linking with $(LD).

The two flags listed above are similar to ccflags-y and asflags-y. The difference is that the subdir- variants have effect for the kbuild file where they are present and all subdirectories. Options specified using subdir-* are added to the commandline before the options specified using the non-subdir variants.

CFLAGS_$@ and AFLAGS_$@ only apply to commands in current kbuild makefile.

$(CFLAGS_$@) specifies per-file options for $(CC). The $@ part has a literal value which specifies the file that it is for.

These two lines specify compilation flags for aha152x.o and gdth.o.

$(AFLAGS_$@) is a similar feature for source files in assembly languages.

3.9 Dependency tracking¶

Kbuild tracks dependencies on the following:

1. All prerequisite files (both *.c and *.h )
2. CONFIG_ options used in all prerequisite files
3. Command-line used to compile target

Thus, if you change an option to $(CC) all affected files will be re-compiled.

3.10 Special Rules¶

Special rules are used when the kbuild infrastructure does not provide the required support. A typical example is header files generated during the build process. Another example are the architecture-specific Makefiles which need special rules to prepare boot images etc.

Special rules are written as normal Make rules. Kbuild is not executing in the directory where the Makefile is located, so all special rules shall provide a relative path to prerequisite files and target files.

Two variables are used when defining special rules:

$(src) $(src) is a relative path which points to the directory where the Makefile is located. Always use $(src) when referring to files located in the src tree. $(obj)

$(obj) is a relative path which points to the directory where the target is saved. Always use $(obj) when referring to generated files.

This is a special rule, following the normal syntax required by make.

The target file depends on two prerequisite files. References to the target file are prefixed with $(obj), references to prerequisites are referenced with $(src) (because they are not generated files).

$(kecho) echoing information to user in a rule is often a good practice but when execution «make -s» one does not expect to see any output except for warnings/errors. To support this kbuild defines $(kecho) which will echo out the text following $(kecho) to stdout except if «make -s» is used.

3.11 $(CC) support functions¶

as-option is used to check if $(CC) — when used to compile assembler ( *.S ) files — supports the given option. An optional second option may be specified if the first option is not supported.

In the above example, cflags-y will be assigned the option -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC). The second argument is optional, and if supplied will be used if first argument is not supported.

cc-ldoption is used to check if $(CC) when used to link object files supports the given option. An optional second option may be specified if first option are not supported.

In the above example, vsyscall-flags will be assigned the option -Wl$(comma)—hash-style=sysv if it is supported by $(CC). The second argument is optional, and if supplied will be used if first argument is not supported.

as-instr as-instr checks if the assembler reports a specific instruction and then outputs either option1 or option2 C escapes are supported in the test instruction Note: as-instr-option uses KBUILD_AFLAGS for assembler options cc-option

cc-option is used to check if $(CC) supports a given option, and if not supported to use an optional second option.

In the above example, cflags-y will be assigned the option -march=pentium-mmx if supported by $(CC), otherwise -march=i586. The second argument to cc-option is optional, and if omitted, cflags-y will be assigned no value if first option is not supported. Note: cc-option uses KBUILD_CFLAGS for $(CC) options

cc-option-yn is used to check if gcc supports a given option and return ‘y’ if supported, otherwise ‘n’.

In the above example, $(biarch) is set to y if $(CC) supports the -m32 option. When $(biarch) equals ‘y’, the expanded variables $(aflags-y) and $(cflags-y) will be assigned the values -a32 and -m32, respectively. Note: cc-option-yn uses KBUILD_CFLAGS for $(CC) options

cc-disable-warning checks if gcc supports a given warning and returns the commandline switch to disable it. This special function is needed, because gcc 4.4 and later accept any unknown -Wno-* option and only warn about it if there is another warning in the source file.

In the above example, -Wno-unused-but-set-variable will be added to KBUILD_CFLAGS only if gcc really accepts it.

cc-ifversion tests the version of $(CC) and equals the fourth parameter if version expression is true, or the fifth (if given) if the version expression is false.

In this example, ccflags-y will be assigned the value -O1 if the $(CC) version is less than 4.2. cc-ifversion takes all the shell operators: -eq, -ne, -lt, -le, -gt, and -ge The third parameter may be a text as in this example, but it may also be an expanded variable or a macro.

cc-cross-prefix is used to check if there exists a $(CC) in path with one of the listed prefixes. The first prefix where there exist a prefix$(CC) in the PATH is returned — and if no prefix$(CC) is found then nothing is returned. Additional prefixes are separated by a single space in the call of cc-cross-prefix. This functionality is useful for architecture Makefiles that try to set CROSS_COMPILE to well-known values but may have several values to select between. It is recommended only to try to set CROSS_COMPILE if it is a cross build (host arch is different from target arch). And if CROSS_COMPILE is already set then leave it with the old value.

3.12 $(LD) support functions¶

ld-option is used to check if $(LD) supports the supplied option. ld-option takes two options as arguments. The second argument is an optional option that can be used if the first option is not supported by $(LD).

4 Host Program support¶

Kbuild supports building executables on the host for use during the compilation stage. Two steps are required in order to use a host executable.

The first step is to tell kbuild that a host program exists. This is done utilising the variable hostprogs-y.

The second step is to add an explicit dependency to the executable. This can be done in two ways. Either add the dependency in a rule, or utilise the variable $(always). Both possibilities are described in the following.

4.1 Simple Host Program¶

In some cases there is a need to compile and run a program on the computer where the build is running. The following line tells kbuild that the program bin2hex shall be built on the build host.

Kbuild assumes in the above example that bin2hex is made from a single c-source file named bin2hex.c located in the same directory as the Makefile.

4.2 Composite Host Programs¶

Host programs can be made up based on composite objects. The syntax used to define composite objects for host programs is similar to the syntax used for kernel objects. $( -objs) lists all objects used to link the final executable.

Objects with extension .o are compiled from the corresponding .c files. In the above example, checklist.c is compiled to checklist.o and lxdialog.c is compiled to lxdialog.o.

Finally, the two .o files are linked to the executable, lxdialog. Note: The syntax -y is not permitted for host-programs.

4.3 Using C++ for host programs¶

kbuild offers support for host programs written in C++. This was introduced solely to support kconfig, and is not recommended for general use.

In the example above the executable is composed of the C++ file qconf.cc — identified by $(qconf-cxxobjs).

If qconf is composed of a mixture of .c and .cc files, then an additional line can be used to identify this.

4.4 Controlling compiler options for host programs¶

When compiling host programs, it is possible to set specific flags. The programs will always be compiled utilising $(HOSTCC) passed the options specified in $(KBUILD_HOSTCFLAGS). To set flags that will take effect for all host programs created in that Makefile, use the variable HOST_EXTRACFLAGS.

To set specific flags for a single file the following construction is used:

It is also possible to specify additional options to the linker.

When linking qconf, it will be passed the extra option «-L$(QTDIR)/lib».

4.5 When host programs are actually built¶

Kbuild will only build host-programs when they are referenced as a prerequisite. This is possible in two ways:

1. List the prerequisite explicitly in a special rule.

The target $(obj)/devlist.h will not be built before $(obj)/gen-devlist is updated. Note that references to the host programs in special rules must be prefixed with $(obj).

When there is no suitable special rule, and the host program shall be built when a makefile is entered, the $(always) variable shall be used.

This will tell kbuild to build lxdialog even if not referenced in any rule.

4.6 Using hostprogs-$(CONFIG_FOO)В¶

A typical pattern in a Kbuild file looks like this:

Kbuild knows about both ‘y’ for built-in and ‘m’ for module. So if a config symbol evaluates to ‘m’, kbuild will still build the binary. In other words, Kbuild handles hostprogs-m exactly like hostprogs-y. But only hostprogs-y is recommended to be used when no CONFIG symbols are involved.

5 Kbuild clean infrastructure¶

«make clean» deletes most generated files in the obj tree where the kernel is compiled. This includes generated files such as host programs. Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always), $(extra-y) and $(targets). They are all deleted during «make clean». Files matching the patterns «.[oas]», «.ko», plus some additional files generated by kbuild are deleted all over the kernel src tree when «make clean» is executed.

Additional files can be specified in kbuild makefiles by use of $(clean-files).

When executing «make clean», the file «crc32table.h» will be deleted. Kbuild will assume files to be in the same relative directory as the Makefile, except if prefixed with $(objtree).

To delete a directory hierarchy use:

This will delete the directory debian in the toplevel directory, including all subdirectories.

To exclude certain files from make clean, use the $(no-clean-files) variable. This is only a special case used in the top level Kbuild file:

Usually kbuild descends down in subdirectories due to «obj-* := dir/», but in the architecture makefiles where the kbuild infrastructure is not sufficient this sometimes needs to be explicit.

The above assignment instructs kbuild to descend down in the directory compressed/ when «make clean» is executed.

To support the clean infrastructure in the Makefiles that build the final bootimage there is an optional target named archclean:

When «make clean» is executed, make will descend down in arch/x86/boot, and clean as usual. The Makefile located in arch/x86/boot/ may use the subdir- trick to descend further down.

Note 1: arch/$(ARCH)/Makefile cannot use «subdir-«, because that file is included in the top level makefile, and the kbuild infrastructure is not operational at that point.

Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will be visited during «make clean».

6 Architecture Makefiles¶

The top level Makefile sets up the environment and does the preparation, before starting to descend down in the individual directories. The top level makefile contains the generic part, whereas arch/$(ARCH)/Makefile contains what is required to set up kbuild for said architecture. To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines a few targets.

When kbuild executes, the following steps are followed (roughly):

1. Configuration of the kernel => produce .config
2. Store kernel version in include/linux/version.h
3. Updating all other prerequisites to the target prepare: — Additional prerequisites are specified in arch/$(ARCH)/Makefile
4. Recursively descend down in all directories listed in init-* core* drivers-* net-* libs-* and build all targets. — The values of the above variables are expanded in arch/$(ARCH)/Makefile.
5. All object files are then linked and the resulting file vmlinux is located at the root of the obj tree. The very first objects linked are listed in head-y, assigned by arch/$(ARCH)/Makefile.
6. Finally, the architecture-specific part does any required post processing and builds the final bootimage. — This includes building boot records — Preparing initrd images and the like

6.1 Set variables to tweak the build to the architecture¶

Generic $(LD) options

Flags used for all invocations of the linker. Often specifying the emulation is sufficient.

Note: ldflags-y can be used to further customise the flags used. See chapter 3.7.

Options for $(LD) when linking vmlinux

LDFLAGS_vmlinux is used to specify additional flags to pass to the linker when linking the final vmlinux image. LDFLAGS_vmlinux uses the LDFLAGS_$@ support.

When $(call if_changed,objcopy) is used to translate a .o file, the flags specified in OBJCOPYFLAGS will be used. $(call if_changed,objcopy) is often used to generate raw binaries on vmlinux.

In this example, the binary $(obj)/image is a binary version of vmlinux. The usage of $(call if_changed,xxx) will be described later.

Default value — see top level Makefile Append or modify as required per architecture.

$(CC) compiler flags

Default value — see top level Makefile Append or modify as required per architecture.

Often, the KBUILD_CFLAGS variable depends on the configuration.

Many arch Makefiles dynamically run the target C compiler to probe supported options:

The first example utilises the trick that a config option expands to ‘y’ when selected.

Assembler options specific for built-in

$(KBUILD_AFLAGS_KERNEL) contains extra C compiler flags used to compile resident kernel code.

Assembler options specific for modules

$(KBUILD_AFLAGS_MODULE) is used to add arch-specific options that are used for assembler.

From commandline AFLAGS_MODULE shall be used (see kbuild.txt).

$(CC) options specific for built-in

$(KBUILD_CFLAGS_KERNEL) contains extra C compiler flags used to compile resident kernel code.

Options for $(CC) when building modules

$(KBUILD_CFLAGS_MODULE) is used to add arch-specific options that are used for $(CC). From commandline CFLAGS_MODULE shall be used (see kbuild.txt).

Options for $(LD) when linking modules

$(KBUILD_LDFLAGS_MODULE) is used to add arch-specific options used when linking modules. This is often a linker script.

From commandline LDFLAGS_MODULE shall be used (see kbuild.txt).

KBUILD_ARFLAGS Options for $(AR) when creating archives

ARCH_CPPFLAGS, ARCH_AFLAGS, ARCH_CFLAGS Overrides the kbuild defaults

6.2 Add prerequisites to archheaders¶

The archheaders: rule is used to generate header files that may be installed into user space by «make header_install».

It is run before «make archprepare» when run on the architecture itself.

6.3 Add prerequisites to archprepare¶

The archprepare: rule is used to list prerequisites that need to be built before starting to descend down in the subdirectories. This is usually used for header files containing assembler constants.

In this example, the file target maketools will be processed before descending down in the subdirectories. See also chapter XXX-TODO that describe how kbuild supports generating offset header files.

6.4 List directories to visit when descending¶

An arch Makefile cooperates with the top Makefile to define variables which specify how to build the vmlinux file. Note that there is no corresponding arch-specific section for modules; the module-building machinery is all architecture-independent.

head-y, init-y, core-y, libs-y, drivers-y, net-y

$(head-y) lists objects to be linked first in vmlinux.

$(libs-y) lists directories where a lib.a archive can be located.

The rest list directories where a built-in.a object file can be located.

$(init-y) objects will be located after $(head-y).

Then the rest follows in this order:

The top level Makefile defines values for all generic directories, and arch/$(ARCH)/Makefile only adds architecture-specific directories.

6.5 Architecture-specific boot images¶

An arch Makefile specifies goals that take the vmlinux file, compress it, wrap it in bootstrapping code, and copy the resulting files somewhere. This includes various kinds of installation commands. The actual goals are not standardized across architectures.

It is common to locate any additional processing in a boot/ directory below arch/$(ARCH)/.

Kbuild does not provide any smart way to support building a target specified in boot/. Therefore arch/$(ARCH)/Makefile shall call make manually to build a target in boot/.

The recommended approach is to include shortcuts in arch/$(ARCH)/Makefile, and use the full path when calling down into the arch/$(ARCH)/boot/Makefile.

«$(Q)$(MAKE) $(build)= » is the recommended way to invoke make in a subdirectory.

There are no rules for naming architecture-specific targets, but executing «make help» will list all relevant targets. To support this, $(archhelp) must be defined.

When make is executed without arguments, the first goal encountered will be built. In the top level Makefile the first goal present is all:. An architecture shall always, per default, build a bootable image. In «make help», the default goal is highlighted with a ‘*’. Add a new prerequisite to all: to select a default goal different from vmlinux.

When «make» is executed without arguments, bzImage will be built.

6.6 Building non-kbuild targets¶

extra-y specifies additional targets created in the current directory, in addition to any targets specified by obj-* .

Listing all targets in extra-y is required for two purposes:

1. Enable kbuild to check changes in command lines
   • When $(call if_changed,xxx) is used
2. kbuild knows what files to delete during «make clean»

In this example, extra-y is used to list object files that shall be built, but shall not be linked as part of built-in.a.

This works as a weaker version of header-test-y, and accepts wildcard patterns. The typical usage is:

This specifies all the files that matches to ‘ * .h’ in the current directory, but the files in ‘header-test-‘ are excluded.

6.7 Commands useful for building a boot image¶

Kbuild provides a few macros that are useful when building a boot image.

if_changed is the infrastructure used for the following commands.

When the rule is evaluated, it is checked to see if any files need an update, or the command line has changed since the last invocation. The latter will force a rebuild if any options to the executable have changed. Any target that utilises if_changed must be listed in $(targets), otherwise the command line check will fail, and the target will always be built. Assignments to $(targets) are without $(obj)/ prefix. if_changed may be used in conjunction with custom commands as defined in 6.8 «Custom kbuild commands».

Note: It is a typical mistake to forget the FORCE prerequisite. Another common pitfall is that whitespace is sometimes significant; for instance, the below will fail (note the extra space after the comma):

WRONG! $(call if_changed, ld/objcopy/gzip/. )

Note: if_changed should not be used more than once per target. It stores the executed command in a corresponding .cmd

file and multiple calls would result in overwrites and unwanted results when the target is up to date and only the tests on changed commands trigger execution of commands.

Link target. Often, LDFLAGS_$@ is used to set specific options to ld.

In this example, there are two possible targets, requiring different options to the linker. The linker options are specified using the LDFLAGS_$@ syntax — one for each potential target. $(targets) are assigned all potential targets, by which kbuild knows the targets and will:

1. check for commandline changes
2. delete target during make clean

The «: %: %.o» part of the prerequisite is a shorthand that frees us from listing the setup.o and bootsect.o files.

Note: It is a common mistake to forget the «targets :=» assignment, resulting in the target file being recompiled for no obvious reason. objcopy Copy binary. Uses OBJCOPYFLAGS usually specified in arch/$(ARCH)/Makefile. OBJCOPYFLAGS_$@ may be used to set additional options. gzip

Compress target. Use maximum compression to compress target.

Create flattened device tree blob object suitable for linking into vmlinux. Device tree blobs linked into vmlinux are placed in an init section in the image. Platform code must copy the blob to non-init memory prior to calling unflatten_device_tree().

To use this command, simply add *.dtb into obj-y or targets, or make some other target depend on %.dtb

A central rule exists to create $(obj)/%.dtb from $(src)/%.dts ; architecture Makefiles do no need to explicitly write out that rule.

6.8 Custom kbuild commands¶

When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand of a command is normally displayed. To enable this behaviour for custom commands kbuild requires two variables to be set:

When updating the $(obj)/bzImage target, the line:

will be displayed with «make KBUILD_VERBOSE=0».

— 6.9 Preprocessing linker scripts

When the vmlinux image is built, the linker script arch/$(ARCH)/kernel/vmlinux.lds is used. The script is a preprocessed variant of the file vmlinux.lds.S located in the same directory. kbuild knows .lds files and includes a rule *lds.S -> *lds .

The assignment to $(always) is used to tell kbuild to build the target vmlinux.lds. The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the specified options when building the target vmlinux.lds.

When building the *.lds target, kbuild uses the variables:

The kbuild infrastructure for *lds files is used in several architecture-specific files.

6.10 Generic header files¶

6.11 Post-link pass¶

If the file arch/xxx/Makefile.postlink exists, this makefile will be invoked for post-link objects (vmlinux and modules.ko) for architectures to run post-link passes on. Must also handle the clean target.

This pass runs after kallsyms generation. If the architecture needs to modify symbol locations, rather than manipulate the kallsyms, it may be easier to add another postlink target for .tmp_vmlinux? targets to be called from link-vmlinux.sh.

For example, powerpc uses this to check relocation sanity of the linked vmlinux file.

7 Kbuild syntax for exported headers¶

The kernel includes a set of headers that is exported to userspace. Many headers can be exported as-is but other headers require a minimal pre-processing before they are ready for user-space. The pre-processing does:

• drop kernel-specific annotations
• drop include of compiler.h
• drop all sections that are kernel internal (guarded by ifdef __KERNEL__ )

7.1 no-export-headers¶

7.2 generic-y¶

If an architecture uses a verbatim copy of a header from include/asm-generic then this is listed in the file arch/$(ARCH)/include/asm/Kbuild like this:

During the prepare phase of the build a wrapper include file is generated in the directory:

When a header is exported where the architecture uses the generic header a similar wrapper is generated as part of the set of exported headers in the directory:

The generated wrapper will in both cases look like the following:

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